In processors (microprocessors and microcontrollers) with a multi-boot memory architecture, the processor has two or more regions of program memory. These regions may represent a logical partitioning of the memory or may represent actual physical partitions. In general, this architecture is defined by the fact that one region of program memory can be updated while the CPU continues to execute out of another region of program memory.
The typical use case for this is to perform an update of a single set of application code while the application is running. This “hot” update is important for “constant run” applications, where any significant downtime of the processor can be problematic.
Once an application and/or the processor determines that a new version of the code is available in another region, it performs a “hot swap,” where transfer of code execution is done from the old region to the new region. This is typically accompanied by a reset of the processor. Such a reset requires a certain amount of time.
More particularly, a typical implementation is to execute from Memory A while updating the program code by writing a complete, new copy of the program image into Memory B. Once the new program image has been written and verified, the MCU/MPU switches over to program execution in the Memory B (the updated program code). Without doing a system reset, this can be a complex operation due to the potential relocation of resources like the stack, heap, program counter, interrupt vector table, etc. However, with a system reset before the switchover, the switchover time is increased, which may not be suitable for constant run applications, such as SMPS (switched mode power supply), motor control, etc.
The total re-boot time is composed of several sequential events, including starting up oscillators/bandgaps/regulators, etc., switching to the correct clock source, setting up the stack, setting up the heap, initializing SRAM, and initializing all peripherals.
For example, shown in FIG. 1 is a schematic illustrating time required for the hot swap. Shown is a timeline 101. Once the new code has booted to a first instruction 102, the stack must be set up 104, the heap must be set up 106, SRAM must be initialized 108, and peripherals must be initialized 110. Only then can the code itself begin to execute 112. As can be appreciated, setting up the stack and the heap, and initializing the SRAM and peripherals can be relatively time-consuming.
Thus, there exists a need for improved switching between memory segments in a hot swappable memory system. There exists a further need to decrease switchover time in such systems.